| 论文编号: | 172511O120100150 |
| 第一作者所在部门: | 九室一组 |
| 论文题目: | 采用SiP技术在硅基interposer上制作PN结电容 |
| 论文题目英文: | |
| 作者: | 戴风伟 |
| 论文出处: | |
| 刊物名称: | 2010 11th International Conference on Electronic Packaging Technology & High Density Packaging |
| 年: | 2010 |
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| 影响因子: | 0 |
| 摘要: | The article relates to the fabrication of embedded P-N junction capacitors, using System-in-Package (SiP) technology, on a silicon interposer wafer with Through- Silicon-Via (TSV). The P-N junction capacitors are fabricated using current micromachining technologies, including etching high aspect-ratio, three-dimensional honeycomb structure and thermal oxidation, thermal dopant diffusion, sputtering, and metallization and so on. The fabricated capacitor displays high capacitance density compared with common twodimensional (2D) P-N junction capacitors. Tests at high frequency (10 MHz-40 GHz) were conducted to evaluate the properties of these capacitors. Test results show that the capacitors have a high capacitance density up to 12nF/mm2 of wafer area, with reverse bias voltage of 1V, which is about 10-12 times that of 2D semiconductor capacitors, and is attributed to the increased junction area inherent in the threedimensional via structure. These capacitors can be used for decoupling under a wide frequency range from 300 MHz to 3.2 GHz. they show a low parasitic inductance by measuring. Capacitor has a characteristic that capacitance value also keeps up constant with the increase of frequency. |
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| 备注: | ICEPT-HDP 2010 |
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