| 论文编号: | 172511O120100193 |
| 第一作者所在部门: | 十一室一组 |
| 论文题目: | 一种小数频综的分数杂散减少技术 |
| 论文题目英文: | |
| 作者: | 黄水龙 |
| 论文出处: | SCI收录 |
| 刊物名称: | Analog Integrated Circuits and Signal Processing |
| 年: | 2010 |
| 卷: | 6 |
| 期: | 3 |
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| 影响因子: | 0.408 |
| 摘要: | A fractional spur suppression technique is presented based on the principle of spur generation, which makes the phase between the divider output and the reference be permanently coherent like integer-N frequency synthesizer, so a real lock is achieved. The spurious tones are strongly reduced without sacrificing the PLL bandwidth. The detailed scheme and corresponding key building blocks are deeply discussed. A 1.9GHz frequency synthesizer with a 100 KHz bandwidth is implemented with the proposed way. SpectreVerilog simulation results show that the technique can reduce over 10dBc/Hz spurious tones. So it is suitable for high spectral purity frequency synthesizer. |
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