| 论文编号: | 172511O120100227 |
| 第一作者所在部门: | 二室四组 |
| 论文题目: | 基于SOI的FPGA逻辑模块的设计与验证 |
| 论文题目英文: | |
| 作者: | 王剑 |
| 论文出处: | EI收录 |
| 刊物名称: | ICSICT2010 |
| 年: | 2010 |
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| 影响因子: | 0 |
| 摘要: | A novel logic block circuit consisting of two multi-mode logic cells is proposed for the design of a tile-based FPGA fabricated with a 0.5μm SOI-CMOS logic process.The proposed 3-LUT based logic cell circuit increases logic density by about 12% compared with a traditional 4-LUT implementation. Comparing with the published data on the CLB in Xilinx Spartan FPGA, the maximum LUT logic propagation delay has about 20% improvement and the Distributed RAM average access time has about 21% improvement. |
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| 备注: | ICSICT2010 |
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