| 论文编号: | 172511O120120206 |
| 第一作者所在部门: | 二室四组 |
| 论文题目: | 基于SOI的FPGA的EDA工具的集成架构 |
| 作者: | 于芳 |
| 刊物名称: | Journal of Electronic Science and Technology |
| 年: | 2012 |
| 卷: | 10 |
| 期: | 1 |
| 页: | 72 |
| 联系作者: | 于芳 |
| 影响因子: | 0.3371 |
| 摘要: | For an SOI-FPGA (silicon-on-insulator field programmable gate arrays) (VS1000) fabricated with 0.5 μm SOI-CMOS (silicon-on-insulator complementary-metal-oxide-semiconductor) process, a complete integrated platform of FPGA computer-aided design (CAD) toolset (VDK) is developed, which can convert the Verilog HDL (hardware description language) description into a bitstream and finally download it into an FPGA. Experiments and testing verify that this FPGA CAD works well and efficiently. |
| 备注: | EI收录 |
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