| 论文编号: | 172511O120120054 |
| 第一作者所在部门: | 一室 |
| 论文题目: | 背栅应力对LOCOS隔离的SOI器件背栅阈值电压的影响 |
| 论文题目英文: | |
| 作者: | 韩郑生 |
| 论文出处: | |
| 刊物名称: | Journal of Semiconductors |
| 年: | 2012 |
| 卷: | |
| 期: | 2 |
| 页: | 024002-1 |
| 联系作者: | 韩郑生 |
| 收录类别: | |
| 影响因子: | 3.844 |
| 摘要: | The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress |
| 英文摘要: | |
| 外单位作者单位: | |
| 备注: | EI收录 |
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