| 论文编号: | 172511O120120183 |
| 第一作者所在部门: | 二室四组 |
| 论文题目: | |
| 论文题目英文: | |
| 作者: | 于芳 |
| 论文出处: | |
| 刊物名称: | Journal of Semiconductors |
| 年: | 2012 |
| 卷: | 33 |
| 期: | 9 |
| 页: | 095005-1 |
| 联系作者: | 于芳 |
| 收录类别: | |
| 影响因子: | 0.579 |
| 摘要: | A 10-bit 50-MS/s reference-free low power successive approximation register(SAR) analog-to-digital converter(ADC) is presented.An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC(CDAC) is implemented to cancel the offset of the latch-type sense amplifier(SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier,so that the power consumption can be reduced further.The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology.At a 1.5-V supply and 50-MS/s with 5-MHz input,the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW,resulting in a figure of merit(FOM) of 61.1 fJ/conversion-step. |
| 英文摘要: | |
| 外单位作者单位: | |
| 备注: | EI收录 |
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