| 论文编号: | 172511O120120086 |
| 第一作者所在部门: | 十室一组 |
| 论文题目: | 22nm后栅工艺CMOS器件先进栅结构应力特征 |
| 论文题目英文: | |
| 作者: | 付作振 |
| 论文出处: | |
| 刊物名称: | ECS Transactions |
| 年: | 2012 |
| 卷: | 44 |
| 期: | 1 |
| 页: | 395 |
| 联系作者: | 付作振 |
| 收录类别: | |
| 影响因子: | 0 |
| 摘要: | In this paper, the characteristics of gate strain enginnering on 22nm High-k/Metal-Gate-last (HK/MG-last) CMOS device are studied through a process and device simulation by Sentarus TCAD tools. Advanced gate architecture with different tensile stress values (0~6GPa) was implemented into the simulation. Besides the traditional stressors like e-GeSi, capping layer and spacer, the stress from advanced gate architecture introduce a new stress effect on carriers tranporting in HK/MG-last device. The parameters optimization for metal gate architecture and material are carried out to maximize channel center strain effect along XX direction, which bring more enhancements on device’s electrical performance. The results indicated that, compared to nitride stress liner, as the scaling of the gate length from 45nm to 22nm node, the channel stress caused by gate stressor is more obvious. |
| 英文摘要: | |
| 外单位作者单位: | |
| 备注: | EI收录 |
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