教育背景
2016.08-2019.08,新加坡国立大学,博士
2013.09-2016.07,中国科学院微电子研究所,硕士
2009.09-2013.08,电子科技大学,学士
工作简历
2022.03-至今,中国科学院微电子研究所,研究员;
2021.01-2022.03,中国科学院微电子研究所,副研究员;
2019.11-2020.11,新加坡国立大学,博士后研究员;
后摩尔EDA器件模型与集成设计方法研究
1. 前沿器件紧凑模型与AI驱动建模算法设计
2. 关键器件物理:可靠性机理与传输机理研究
3. 异质集成芯片设计与EDA-D/STCO方法
1)国家重点研发计划课题, 2021YFB3600704,在研,主持(2021-2025)
2) 国家高层次青年人才项目, 在研,主持(2022-2024)
3)国家自然科学基金委员会面上项目,62274178,在研,主持(2023-2026)
4) 集成电路先进器件工艺仿真与智能EDA青年交叉团队, JCTD-2022-07, 在研,参与(2023-2025)
[1] Xufan Li, Zhenhua Wu, Gerhard Rzepa, Markus Karner, Haoqing Xu, Zhicheng Wu, Wei Wang, Guanhua Yang, Qing Luo*, Lingfei Wang* and Ling Li*. "Overview of emerging semiconductor device model methodologies: From device physics to machine learning engines", Fundamental Research, 2024.
[2] Lihua Xu, Kaifei Chen, Zhi Li, Jingrui Guo, Linfang Wang, Yue Zhao, Shijie Huang, Zhidao Zhou, Chunmeng Dou*, Guanhua Yang*, Lingfei Wang*, Ling Li and Ming Liu. "Reliability-Aware Ultra-Scaled IDG-InGaZnO-FET Compact Model to Enable Cross-layer Co-design for Highly Efficient Analog Computing in 2T0C-DRAM"[C]//2023 International Electron Devices Meeting (IEDM). IEEE.
[3] Tiancheng Gong, Lihua Xu, Wei Wei, Pengfei Jiang, Peng Yuan, Bowen Nie, Yuanquan Huang, Yuan Wang, Yang Yang, Jianfeng Gao, Junfeng Li, Jun Luo, Lingfei Wang*, Jianguo Yang*, Qing Luo*, Ling Li, Steve S Chung, Ming Liu, "First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip", in 2023 Symposium on VLSI Technology, IEEE, 2023.
[4] Jingrui Guo, Ying Sun, Lingfei Wang*, Xinlv Duan, Kailiang Huang, Zhaogui Wang, Junxiao Feng, Qian Chen, Shijie Huang, Lihua Xu, Di Geng, Guangfan Jiao, Shihui Yin, Zhengbo Wang, Weiliang Jing*, Ling Li* and Ming Liu. "Compact Modeling of IGZO-based CAA-FETs with Time-zero-instability and BTI Impact on Device and Capacitor-less DRAM Retention Reliability," in 2022 Symposium on VLSI Technology, IEEE, 2022.
[5] Shijie Huang, Zhenhua Wu, Haoqing Xu, Jingrui Guo, Lihua Xu, Xinlv Duan, Qian Chen, Guanhua Yang, Qingzhu Zhang, Huaxiang Yin, Lingfei Wang*, Ling Li* and Ming Liu, "Geometric Variability Aware Quantum Potential based Quasi-ballistic Compact Model for Stacked 6 nm-Thick Silicon Nanosheet GAA-FET", in 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 18.5. 1-18.5. 4.
[6] Jingrui Guo, Kaizhen Han, Subhali Subhechha, Xinlv Duan, Qian Chen Di Geng, Shijie Huang, Lihua Xu, Junjie An, Gouri Sankar Kar, Xiao Gong, Lingfei Wang*, Ling Li*, Ming Liu, "A New Surface Potential and Physics Based Compact Model for a-IGZO TFTs at Multinanoscale for High Retention and Low-Power DRAM Application", in 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 8.5. 1-8.5. 4.
[7] Ying Zhao,Lingfei Wang*, Zhenhua Wu, Franz Schanovsky Xiaoxin Xu, Hong Yang, Hao Yu, Jinru Lai, Donyang Liu, Xichen Chuai, Yue Su, Xingsheng Wang, Ling Li* and Ming Liu*. "A Unified Physical BTI Compact Model in Variability-Aware DTCO Flow: Device Characterization and Circuit Evaluation on Reliability of Scaling Technology Nodes," in 2021 Symposium on VLSI Technology, pp. 1-2. IEEE, 2021.
[8] Lingfei Wang*, Lin Wang, Kah-Wee Ang, Aaron Thean, and Gengchiau Liang*, “A Surface Potential- and Physics- Based Compact Model for 2D Polycrystalline-MoS2 FET with Resistive Switching Behavior in Neuromorphic Computing,” in 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 24.5. 1-24.5. 4.
[9] Lingfei Wang, Yang Li, Xuewei Feng, Kah-Wee Ang, Xiao Gong, Aaron Thean, and Gengchiau Liang, “A unified surface potential based physical compact model for both unipolar and ambipolar 2D-FET: Experimental verification and circuit demonstration,” in 2017 IEEE International Electron Devices Meeting (IEDM), 2017, pp. 31.4. 1-31.4. 4.
[10] Lingfei Wang, Songang Peng, Zhiwei Zong, Ling Li, Wei Wang, Guangwei Xu, Nianduan Lu, Zhuoyu Ji, Zhi Jin, and Ming Liu, “A new surface potential based physical compact model for GFET in RF applications,” in 2015 IEEE International Electron Devices Meeting (IEDM), 2015, pp. 28.4. 1-28.4. 4.
人才队伍