教育背景
2017.08–2021.06：澳门大学，电机及电脑工程，博士
2014.09–2017.07：中国科学院大学，电子与通信工程，硕士
2010.09–2014.07：青岛大学，微电子学，学士
工作简历
2023.06–至今：中国科学院微电子研究所，研究员，课题组长
2023.04–2023.06：中国科学院微电子研究所，副研究员，课题组长
2021.07–2023.03：东京大学，特任研究员
模拟、射频、混合信号集成电路设计
硅基射频、毫米波、太赫兹通信芯片设计
硅基压控振荡器、锁相环、收发机芯片设计
功率放大器、低噪声放大器、滤波器等射频前端电路设计
1、国家青年人才项目，项目负责人，2024.01–2026.12
2、中国科学院青年人才项目，项目负责人，2024.01–2026.12
3、所长基金项目，项目负责人，2023.01–2025.12
论文
[1] Masaru Osada, Zule Xu, Zunsong Yang, and Tetsuya Iizuka, "A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division with Phase-Domain Filtering," IEEE Journal of Soli-State Circuits (JSSC), 2024.
[2] Yunbo Huang, Yong Chen, Zunsong Yang, Rui P. Martins, and Pui-In Mak, "A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and −74.2dBc Reference Spur," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 2024.
[3] Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak and Rui P. Martins, "A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving −252.9dB Jitter-Power FoM And −63dBc Reference Spur," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, pp. 270-272, Feb. 2019.
[4] Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, and Tetsuya Iizuka, "A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load," IEEE Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan, June 2023.
[5] Zunsong Yang, Zule Xu, Masaru Osada and Tetsuya Iizuka, "A 10-GHz Inductorless Cascaded PLL with Zero-ISF Sub-Sampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter And −240-dB FOMjitter," IEEE Symposium on VLSI Technology and Circuits (VLSI), Hawaii, USA, pp. 10-11, June 2022.
[6] Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, pp. 283-284, Nov. 2019.
[7] Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A 0.003-mm2 440fsRMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 68, no. 6, pp. 2307-2316, June 2021.
[8] Zunsong Yang, Yong Chen, Pui-In Mak and Rui P. Martins, "A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL with −78.7-dBc REF Spur, −128.1-dBc/Hz Absolute In-Band PN and −254-dB FOM," IEEE Solid-State Circuits Letters (SSC-L), vol. 3, pp. 494-497, Oct. 2020.
[9] Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak and Rui P. Martins, "A 3.3-GHz Integer-N Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 30, no. 2, pp. 238-242, Feb. 2022.
书籍/章节
Hao Guo, Zunsong Yang, Chee Cheow Lim, Harikrishnan Ramiah, Yatao Peng, Yong Chen, Jun Yin, Pui-In Mak & Rui P. Martins, Power-Efficient RF and mm-Wave VCOs/PLL, in Mixed-Signal Circuits in Nanoscale CMOS, Analog Circuits and Signal Processing, Springer, 2023.
国家海外高层次人才引进计划入选者
中国科学院高层次人才引进计划入选者
人才队伍